International Workshop on Machine Learning Hardware (IWMLH)
(in submission to ISC2020)
June 25 - Messe Frankfurt, Germany
Recent years have seen a surge of investment in AI chip companies worldwide. Most companies design accelerators for industrial applications, as opposed to scientific workloads. As the use of machine learning (ML) accelerates in the HPC field itself, there is concern that the scientific community should influence the design of this new specialized hardware. Indeed, scientific computing has an uncommon set of requirements regarding platform usage and administration, and how those chips answer those demands will shape the future of their integration within the global scientific computing infrastructure.
The workshop will feature the participation of select AI accelerator companies, with discussions centered on the following aspects:
- Programming models. Most AI chips are designed to leverage regularity in the dataflow inherent in ML models. This design supposes the use of standard model representation formats and/or custom dataflow graph formats. Those programming models are of high interest to the scientific community. We need to understand which types of ML/scientific applications will be supported by each platform, as well as the associated development and maintenance costs.
- Compiler toolchain. ML accelerators often rely on complex compilation technology to map dataflow descriptions to hardware. These compilers can be radically different from existing compiler stacks in that they may solve complex placement and routing problems. The usage model of those compiler toolchains in a scientific computing context is a subject worthy of discussion. Indeed, the features of the compilers and constraints around their use will play a large role in the scientific process itself.
- System interfaces. Understanding what low-level system interfaces will be available can help cast light on which usage and administration model to expect. In particular, we’d like participants to discuss expected capabilities in terms of concurrency, partitioning, debugging, power management, and performance characterization.
- Architecture. Successful integration of AI chips in the existing scientific computing infrastructure will require a proper understanding of chips in terms of operator optimization and customization, bandwidth, latency, memory management, power demands, and network capabilities.
||Albert Cohen, Research Scientist, Google Research.
||Adrian Macias, Machine Learning Systems Specialist
||To be announced
||Matt Fyles, VP of Software
||Andy Hock, Product Management Director
||Yusuke Doi, VP of Computing Infrastructure
Pete Beckman, Argonne National Laboratory -
Swann Perarnau, Argonne National Laboratory -
Rosa M.Badia, Barcelona Supercomputing Center
Kentaro Sano, RIKEN
Valentin Reis, Argonne National Laboratory -